DMA1RSEL=DATA1, DMA1MODE=FULL, INCWIDTH=INCWIDTH1, DMA0RSEL=DATA0, DMA0MODE=FULL
Control Register
| AES | AES Mode |
| KEYBUFDIS | Key Buffer Disable |
| SHA | SHA Mode |
| NOBUSYSTALL | No Stalling of Bus When Busy |
| INCWIDTH | Increment Width 0 (INCWIDTH1): Byte 15 in DATA1 is used for the increment function. 1 (INCWIDTH2): Bytes 14 and 15 in DATA1 are used for the increment function. 2 (INCWIDTH3): Bytes 13 to 15 in DATA1 are used for the increment function. 3 (INCWIDTH4): Bytes 12 to 15 in DATA1 are used for the increment function. |
| DMA0MODE | DMA0 Read Mode 0 (FULL): Target register is fully read/written during every DMA transaction 1 (LENLIMIT): Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing. 2 (FULLBYTE): Target register is fully read/written during every DMA transaction. Bytewise DMA. 3 (LENLIMITBYTE): Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing. |
| DMA0RSEL | DMA0 Read Register Select 0 (DATA0): undefined 1 (DDATA0): undefined 2 (DDATA0BIG): undefined 3 (QDATA0): undefined |
| DMA1MODE | DMA1 Read Mode 0 (FULL): Target register is fully read/written during every DMA transaction 1 (LENLIMIT): Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing. 2 (FULLBYTE): Target register is fully read/written during every DMA transaction. Bytewise DMA. 3 (LENLIMITBYTE): Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing. |
| DMA1RSEL | DATA0 DMA Unaligned Read Register Select 0 (DATA1): undefined 1 (DDATA1): undefined 2 (QDATA1): undefined 3 (QDATA1BIG): undefined |
| COMBDMA0WEREQ | Combined Data0 Write DMA Request |